Hi, Rob
Thanks for your review.
On 2025/1/4 2:55, Rob Herring wrote:
[ EXTERNAL EMAIL ]
On Tue, Dec 31, 2024 at 02:00:43PM +0800, Jian Hu wrote:
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
---
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 115 ++++++++++++++++++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 +++++++++
2 files changed, 172 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
new file mode 100644
index 000000000000..f90e6021d298
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2024 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@xxxxxxxxxx>
+ - Jerome Brunet <jbrunet@xxxxxxxxxxxx>
+ - Jian Hu <jian.hu@xxxxxxxxxxx>
+ - Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-pll-gp0
+ - amlogic,t7-pll-gp1
+ - amlogic,t7-pll-hifi
+ - amlogic,t7-pll-pcie
+ - amlogic,t7-mpll
+ - amlogic,t7-pll-hdmi
+ - amlogic,t7-pll-mclk
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-pll-gp0
+ - amlogic,t7-pll-gp1
+ - amlogic,t7-pll-hifi
+ - amlogic,t7-pll-pcie
+ - amlogic,t7-mpll
+ - amlogic,t7-pll-hdmi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: pll input oscillator gate
+
+ clock-names:
+ items:
+ - const: input
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-pll-mclk
+ then:
+ properties:
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: 24M oscillator input clock source for mclk_sel_0
+ - description: fix 50Mhz input clock source for mclk_sel_0
+
+ clock-names:
+ items:
+ - const: input
+ - const: mclk_in0
+ - const: mclk_in1
Define the names and descriptions at the top level. Then here just say
'minItems: 3'
ok , I will refer to
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml and
update T7 PLL yaml for it.
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gp0:clock-controller@8080 {
Drop unused labels.
ok, I will remove the two labels in v2 patch.
+ compatible = "amlogic,t7-pll-gp0";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "input";
+ #clock-cells = <1>;
+ };
+
+ mclk:clock-controller@8300 {
+ compatible = "amlogic,t7-pll-mclk";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "input", "mclk_in0", "mclk_in1";
+ #clock-cells = <1>;
+ };
+ };
--
2.47.1
