On 07/01/2025 14:51, Jessica Clarke wrote:
> On 7 Jan 2025, at 14:34, Vincenzo Frascino <vincenzo.frascino@xxxxxxx> wrote:
>>
>> Hi Jessica,
>>
>> Thank you for your review.
>>
>> On 07/01/2025 12:56, Jessica Clarke wrote:
>>> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote:
>>>> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
>>>> <vincenzo.frascino@xxxxxxx> wrote:
>>>>> + cpus {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + cpu0: cpu@0 {
>>>>> + compatible = "arm,neoverse-n1";
>>>>
>>>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
>>>> "arm,neoverse-n1-morello" if we want to capture what it is derived
>>>> from and since "arm,morello" is taken already.
>>>
>>> Rainier is the codename of the core itself, and Morello LLVM recognises
>>> -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so
>>> perhaps it should really be "arm,rainier". Though SMBIOS reports it as
>>> Morello-R0P1 so it may be best to use "arm,morello" here.
>>>
>>
>> We agree on the concept. It should either be "arm,rainier" or "arm,morello-r0p1"
>
> r0p1 isn’t right. Boards with r0p0 and r0p2 CPUs also exist (although
> the former are now only within Arm, but the latter are in the wild in
> limited numbers, including a couple here at Cambridge).
>
Agreed, my proposals were in order of preference. "arm,rainier" seems the best
choice. Let's see what Rob thinks.
[...]
--
Regards,
Vincenzo
