From: Rohit Visavalia <rohit.visavalia@xxxxxxxxxx>
Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
- move xlnx_vcu DT binding to clock from soc following commit
a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc")
- corrected clock sequence as per xilinx device-tree generator
Signed-off-by: Rohit Visavalia <rohit.visavalia@xxxxxxxxxx>
---
Changes in v2:
- dropped patch 1 and move the file during conversion
- dropped description in schema
- updated commit msg for change in clock ordering
---
.../devicetree/bindings/clock/xlnx,vcu.yaml | 55 +++++++++++++++++++
.../bindings/soc/xilinx/xlnx,vcu.txt | 26 ---------
2 files changed, 55 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
delete mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
new file mode 100644
index 000000000000..02d27d11a452
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: LogicoreIP designed compatible with Xilinx ZYNQ family.
+
+maintainers:
+ - Rohit Visavalia <rohit.visavalia@xxxxxxx>
+
+description:
+ LogicoreIP design to provide the isolation between processing system
+ and programmable logic. Also provides the list of register set to configure
+ the frequency.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,vcu
+ - xlnx,vcu-logicoreip-1.0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: pll ref clocksource
+ - description: aclk
+
+ clock-names:
+ items:
+ - const: pll_ref
+ - const: aclk
+
+required:
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ fpga {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ xlnx_vcu: vcu@a0040000 {
+ compatible = "xlnx,vcu-logicoreip-1.0";
+ reg = <0x0 0xa0040000 0x0 0x1000>;
+ clocks = <&si570_1>, <&clkc 71>;
+ clock-names = "pll_ref", "aclk";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
deleted file mode 100644
index 2417b13ba468..000000000000
--- a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-LogicoreIP designed compatible with Xilinx ZYNQ family.
--------------------------------------------------------
-
-General concept
----------------
-
-LogicoreIP design to provide the isolation between processing system
-and programmable logic. Also provides the list of register set to configure
-the frequency.
-
-Required properties:
-- compatible: shall be one of:
- "xlnx,vcu"
- "xlnx,vcu-logicoreip-1.0"
-- reg : The base offset and size of the VCU_PL_SLCR register space.
-- clocks: phandle for aclk and pll_ref clocksource
-- clock-names: The identification string, "aclk", is always required for
- the axi clock. "pll_ref" is required for pll.
-Example:
-
- xlnx_vcu: vcu@a0040000 {
- compatible = "xlnx,vcu-logicoreip-1.0";
- reg = <0x0 0xa0040000 0x0 0x1000>;
- clocks = <&si570_1>, <&clkc 71>;
- clock-names = "pll_ref", "aclk";
- };
--
2.25.1
