On 1/4/2025 1:10 PM, Dmitry Baryshkov wrote: > On Mon, Dec 30, 2024 at 01:13:08PM +0530, Akhil P Oommen wrote: >> On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote: >>> On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote: >>>> >>>> >>>> On 26/10/2024 23:42, Dmitry Baryshkov wrote: >>>>> From: Naman Jain <quic_namajain@xxxxxxxxxxx> >>>>> >>>>> Add logic for alignment of address for reading in qfprom driver to avoid >>>>> NOC error issues due to unaligned access. The problem manifests on the >>>>> SAR2130P platform, but in msm-5.x kernels the fix is applied >>>> >>>> Is this only issue with SAR2130P? >> >> This is applicable to all chipsets with sys arch newer than Snapdragon 8 >> Gen 1. >> >>> >>> I don't know. I know that it manifests on SAR2130P, but in the vendor >>> kernels the fix is applied to all the platforms. >>> >>>> >>>>> uncoditionally. Follow this approach and uncoditionally perform aligned >>>>> reads. >>>> >>>> If there is a need of having proper register alignment this should go as >>>> part of the nvmem_config->stride and word_size configuration and not in >>>> reg_read callbacks. >>> >>> Thanks, I'll explore that option. Indeed, it might be easier to handle. >> >> Dmitry, any update here? I need similar change for X1E GPU speedbin support. > > Excuse me for the delay, I've sent v3, reworking the series as > requested: > > https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@xxxxxxxxxx/ > No issues. Thanks a lot for getting this done. -Akhil.
