USIv1 IP-core is found on some ARM64 Exynos SoCs (like Exynos8895) and
provides selectable serial protocols (one of: HSI2C0, HSI2C1, HSI2C0_1,
SPI, UART, UART_HSI2C1).
USIv1, unlike USIv2, doesn't have any known register map. Underlying
protocols that it implements have no offset, like with Exynos850.
Desired protocol can be chosen via SW_CONF register from System
Register block of the same domain as USI.
In order to select a particular protocol, the protocol has to be
selected via the System Register. Unlike USIv2, there's no need for
any setup before the given protocol becomes accessible apart from
enabling the APB clock and the protocol operating clock.
Modify the existing driver in order to allow USIv1 to probe and set
its protocol.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
---
drivers/soc/samsung/exynos-usi.c | 42 +++++++++++++++++++++++++++++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c
index 114352695..e57d2c274 100644
--- a/drivers/soc/samsung/exynos-usi.c
+++ b/drivers/soc/samsung/exynos-usi.c
@@ -16,6 +16,18 @@
#include <dt-bindings/soc/samsung,exynos-usi.h>
+/* USIv1: System Register: SW_CONF register bits */
+#define USI_V1_SW_CONF_NONE 0x0
+#define USI_V1_SW_CONF_I2C0 0x1
+#define USI_V1_SW_CONF_I2C1 0x2
+#define USI_V1_SW_CONF_I2C0_1 0x3
+#define USI_V1_SW_CONF_SPI 0x4
+#define USI_V1_SW_CONF_UART 0x8
+#define USI_V1_SW_CONF_UART_I2C1 0xa
+#define USI_V1_SW_CONF_MASK (USI_V1_SW_CONF_I2C0 | USI_V1_SW_CONF_I2C1 | \
+ USI_V1_SW_CONF_I2C0_1 | USI_V1_SW_CONF_SPI | \
+ USI_V1_SW_CONF_UART | USI_V1_SW_CONF_UART_I2C1)
+
/* USIv2: System Register: SW_CONF register bits */
#define USI_V2_SW_CONF_NONE 0x0
#define USI_V2_SW_CONF_UART BIT(0)
@@ -34,7 +46,8 @@
#define USI_OPTION_CLKSTOP_ON BIT(2)
enum exynos_usi_ver {
- USI_VER2 = 2,
+ USI_VER1 = 1,
+ USI_VER2,
};
struct exynos_usi_variant {
@@ -71,6 +84,13 @@ static const struct exynos_usi_mode exynos_usi_modes[] = {
[USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART },
[USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI },
[USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C },
+ [USI_V1_NONE] = { .name = "none", .val = USI_V1_SW_CONF_NONE },
+ [USI_V1_I2C0] = { .name = "i2c0", .val = USI_V1_SW_CONF_I2C0 },
+ [USI_V1_I2C1] = { .name = "i2c1", .val = USI_V1_SW_CONF_I2C1 },
+ [USI_V1_I2C0_1] = { .name = "i2c0_1", .val = USI_V1_SW_CONF_I2C0_1 },
+ [USI_V1_SPI] = { .name = "spi", .val = USI_V1_SW_CONF_SPI },
+ [USI_V1_UART] = { .name = "uart", .val = USI_V1_SW_CONF_UART },
+ [USI_V1_UART_I2C1] = { .name = "uart_i2c1", .val = USI_V1_SW_CONF_UART_I2C1 },
};
static const char * const exynos850_usi_clk_names[] = { "pclk", "ipclk" };
@@ -83,11 +103,24 @@ static const struct exynos_usi_variant exynos850_usi_data = {
.clk_names = exynos850_usi_clk_names,
};
+static const struct exynos_usi_variant exynos8895_usi_data = {
+ .ver = USI_VER1,
+ .sw_conf_mask = USI_V1_SW_CONF_MASK,
+ .min_mode = USI_V1_NONE,
+ .max_mode = USI_V1_UART_I2C1,
+ .num_clks = ARRAY_SIZE(exynos850_usi_clk_names),
+ .clk_names = exynos850_usi_clk_names,
+};
+
static const struct of_device_id exynos_usi_dt_match[] = {
{
.compatible = "samsung,exynos850-usi",
.data = &exynos850_usi_data,
},
+ {
+ .compatible = "samsung,exynos8895-usi",
+ .data = &exynos8895_usi_data,
+ },
{ } /* sentinel */
};
MODULE_DEVICE_TABLE(of, exynos_usi_dt_match);
@@ -169,9 +202,12 @@ static int exynos_usi_configure(struct exynos_usi *usi)
return ret;
if (usi->data->ver == USI_VER2)
- return exynos_usi_enable(usi);
+ ret = exynos_usi_enable(usi);
+ else
+ ret = clk_bulk_prepare_enable(usi->data->num_clks,
+ usi->clks);
- return 0;
+ return ret;
}
static int exynos_usi_parse_dt(struct device_node *np, struct exynos_usi *usi)
--
2.43.0
