On 03/01/2025 08:31, Luo Jie wrote: > The CMN PLL controller provides clocks to networking hardware blocks > and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the > on-chip Wi-Fi, and produces output clocks at fixed rates. These output > rates are predetermined, and are unrelated to the input clock rate. > The primary purpose of CMN PLL is to supply clocks to the networking > hardware such as PPE (packet process engine), PCS and the externally > connected switch or PHY device. The CMN PLL block also outputs fixed > rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep > clock supplied to GCC. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
