On Thu, Jan 2, 2025 at 11:31 PM Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote: > > On 02/01/2025 18:44, Shubhrajyoti Datta wrote: > > + > > +maintainers: > > + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> > > + > > +description: > > + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 > > + compact and extended memory interfaces. Versal NET DDR memory controller has an optional ECC support > > Please wrap code according to coding style (checkpatch is not a coding > style description, but only a tool). Will fix . > > > > + which correct single bit ECC errors and detect double bit ECC errors. > > + It also has support for reporting other errors like MMCM (Mixed-Mode Clock > > + Manager) errors and General software errors. > > + > > +properties: > > + compatible: > > + const: amd,versal-net-ddrmc5-1.0 > > 1.0 looks redundant. Usually SoC does not change... Anyway, commit msg > should explain why 1.0 is needed (IOW, why exception is justified). > > > + I will change it to const: amd,versal-net-ddrmc5 instead.
