On Thu, 26 Dec 2024 11:30:42 +0530, Thippeswamy Havalige wrote: > Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> > --- > Changes in v2: > ------------- > - Modify patch subject. > - Add pcie host bridge reference. > - Modify filename as per compatible string. > - Remove standard PCI properties. > - Modify interrupt controller description. > - Indentation > > Changes in v3: > ------------- > - Modified SLCR to lower case. > - Add dwc schemas. > - Remove common properties. > - Move additionalProperties below properties. > - Remove ranges property from required properties. > - Drop blank line. > - Modify pci@ to pcie@ > > Changes in v4: > ------------- > - None. > > Changes in v5: > ------------- > - None. > Changes in v6: > -------------- > - Reduce dbi size to 4k. > - update register name to slcr. > --- > .../bindings/pci/amd,versal2-mdb-host.yaml | 121 +++++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
