Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> --- Changes in v2: - rename EDAC to memory controller - update the compatible name - Add remote proc handle - Read the data width from the registers - Remove the dwidth, rank and channel number the same is read from the RpMsg. .../amd,versalnet-ddrmc.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versalnet-ddrmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-ddrmc.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-ddrmc.yaml new file mode 100644 index 000000000000..b6fc3548017d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-ddrmc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/amd,versalnet-ddrmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal NET DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + It also has support for reporting other errors like MMCM (Mixed-Mode Clock + Manager) errors and General software errors. + +properties: + compatible: + const: amd,versalnet-ddrmc + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible = "amd,versalnet-ddrmc"; + amd,rproc = <&remoteproc_r5>; + }; -- 2.17.1
