On Wed, Nov 20, 2024 at 05:49:43PM +0800, Pengfei Li wrote:
> The i.MX 91 family features an Arm Cortex-A55 running at up to
> 1.4GHz, support for modern LPDDR4 memory to enable platform longevity,
> along with a rich set of peripherals targeting medical, industrial
> and consumer IoT market segments.
>
> The design of the i.MX91 platform is very similar to i.MX93.
> The mainly difference between i.MX91 and i.MX93 is as follows:
> - i.MX91 removed some clocks and modified the names of some clocks.
> - i.MX91 only has one A core
> - i.MX91 has different pinmux
>
> Signed-off-by: Pengfei Li <pengfei.li_1@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx91.dtsi | 70 ++
> 2 files changed, 840 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi
...
> diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi
> new file mode 100644
> index 000000000000..be923e5076a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include "imx91-pinfunc.h"
> +#include "imx93.dtsi"
> +
> +/delete-node/ &A55_1;
> +/delete-node/ &cm33;
> +/delete-node/ &mlmix;
> +/delete-node/ &mu1;
> +/delete-node/ &mu2;
> +
> +&clk {
> + compatible = "fsl,imx91-ccm";
> +};
> +
> +&eqos {
> + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> + <&clk IMX91_CLK_ENET_TIMER>,
> + <&clk IMX91_CLK_ENET1_QOS_TSN>,
> + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
Can we align the lines at '<'?
clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
> + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> + <&clk IMX91_CLK_ENET1_QOS_TSN>;
> + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> +};
> +
> +&fec {
> + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> + <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> + <&clk IMX91_CLK_ENET_TIMER>,
> + <&clk IMX91_CLK_ENET2_REGULAR>,
> + <&clk IMX93_CLK_DUMMY>;
> + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> + <&clk IMX91_CLK_ENET2_REGULAR>;
> + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> + assigned-clock-rates = <100000000>, <250000000>;
> +};
> +
> +&i3c1 {
> + clocks = <&clk IMX93_CLK_BUS_AON>,
> + <&clk IMX93_CLK_I3C1_GATE>,
> + <&clk IMX93_CLK_DUMMY>;
> +};
> +
> +&i3c2 {
> + clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
> + <&clk IMX93_CLK_I3C2_GATE>,
> + <&clk IMX93_CLK_DUMMY>;
> +};
> +
> +&iomuxc {
> + compatible = "fsl,imx91-iomuxc";
> +};
> +
> +&tmu {
> + status = "disabled";
> +};
> +
> +&{/soc@0/ddr-pmu@4e300dc0} {
> + compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
> +};
> +
> +&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
> + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +};
Could you add labels in imx93.dtsi to make the references a bit easier?
Shawn
> --
> 2.34.1
>
