On Thu, Dec 26, 2024 at 11:06:48AM +0800, Yijie Yang wrote: > > > On 2024-12-26 01:49, Andrew Lunn wrote: > > On Wed, Dec 25, 2024 at 06:04:44PM +0800, Yijie Yang wrote: > > > The Ethernet MAC requires precise sampling times at Rx, but signals on the > > > Rx side after transmission on the board may vary due to different hardware > > > layouts. The RGMII_CONFIG2_RX_PROG_SWAP can be used to switch the sampling > > > occasion between the rising edge and falling edge of the clock to meet the > > > sampling requirements. > > > > The RGMII specification says that RD[3:0] pins are sampled on the > > rising edge for bits 3:0 and falling edge for bits 7:4. > > > > Given this is part of the standard, why would you want to do anything > > else? > > > > Is this maybe another symptom of having the RGMII delays messed up? > > > > Anyway, i don't see a need for this property, unless you are working > > with a PHY which breaks the RGMII standard, and has its clock > > reversed? > > Please correct me if there are any errors. As described in the Intel and TI > design guidelines, Dual Data Rate (DDR), which samples at both edges of the > clock, is primarily used for 1Gbps speeds. For 100Mbps and 10Mbps speeds, > Single Data Rate (SDR), which samples at the rising edge of the clock, is > typically adopted. If it is typically adopted, why do you need to support falling edge? Because we can is not a good reason. Do you have a board with a PHY which requires falling edge for some reason? Andrew
