The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Add support for
the i.MX8M variant of the IP with this register shift and additional
clock.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Fabio Estevam <festevam@xxxxxxxxx>
Cc: Jaroslav Kysela <perex@xxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Liam Girdwood <lgirdwood@xxxxxxxxx>
Cc: Mark Brown <broonie@xxxxxxxxxx>
Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
Cc: Michael Walle <michael@xxxxxxxx>
Cc: Nicolin Chen <nicoleotsuka@xxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: Shengjiu Wang <shengjiu.wang@xxxxxxxxx>
Cc: Stephen Boyd <sboyd@xxxxxxxxxx>
Cc: Takashi Iwai <tiwai@xxxxxxxx>
Cc: Xiubo Li <Xiubo.Lee@xxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: linux-clk@xxxxxxxxxxxxxxx
Cc: linux-sound@xxxxxxxxxxxxxxx
---
V2: Update commit message, align it with the bindings one
---
drivers/clk/Kconfig | 2 +-
drivers/clk/clk-fsl-sai.c | 22 ++++++++++++++++++----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 713573b6c86c7..575743d7e2c71 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,7 @@ config COMMON_CLK_FSL_FLEXSPI
config COMMON_CLK_FSL_SAI
bool "Clock driver for BCLK of Freescale SAI cores"
- depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST
help
This driver supports the Freescale SAI (Synchronous Audio Interface)
to be used as a generic clock output. Some SoCs have restrictions
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index cba45e07562da..628e53a3a26fa 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -26,9 +26,14 @@ struct fsl_sai_clk {
spinlock_t lock;
};
+struct fsl_sai_data {
+ unsigned int offset; /* Register offset */
+};
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ const struct fsl_sai_data *data = device_get_match_data(dev);
struct fsl_sai_clk *sai_clk;
struct clk_parent_data pdata = { .index = 0 };
void __iomem *base;
@@ -44,17 +49,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + I2S_CSR;
+ sai_clk->gate.reg = base + data->offset + I2S_CSR;
sai_clk->gate.bit_idx = CSR_BCE_BIT;
sai_clk->gate.lock = &sai_clk->lock;
- sai_clk->div.reg = base + I2S_CR2;
+ sai_clk->div.reg = base + data->offset + I2S_CR2;
sai_clk->div.shift = CR2_DIV_SHIFT;
sai_clk->div.width = CR2_DIV_WIDTH;
sai_clk->div.lock = &sai_clk->lock;
/* set clock direction, we are the BCLK master */
- writel(CR2_BCD, base + I2S_CR2);
+ writel(CR2_BCD, base + data->offset + I2S_CR2);
hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
&pdata, 1, NULL, NULL,
@@ -69,8 +74,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
+static const struct fsl_sai_data fsl_sai_vf610_data = {
+ .offset = 0,
+};
+
+static const struct fsl_sai_data fsl_sai_imx8mq_data = {
+ .offset = 8,
+};
+
static const struct of_device_id of_fsl_sai_clk_ids[] = {
- { .compatible = "fsl,vf610-sai-clock" },
+ { .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data },
+ { .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data },
{ }
};
MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
--
2.45.2
