On Sun, Dec 22, 2024 at 09:58:39AM +0100, Linus Walleij wrote: > On Fri, Dec 13, 2024 at 6:32 PM J. Neuschäfer via B4 Relay > <devnull+j.ne.posteo.net@xxxxxxxxxx> wrote: > > > From: "J. Neuschäfer" <j.ne@xxxxxxxxxx> > > > > The Fairchild MM74HC595 and other compatible parts have a latch clock > > input (also known as storage register clock input), which must be > > clocked once in order to apply any value that was serially shifted in. > > > > This patch adds driver support for using a GPIO that connects to the > > latch clock. > > > > Signed-off-by: J. Neuschäfer <j.ne@xxxxxxxxxx> > > This looks completely reasonable to me as far as 2/4 gets merged: > Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx> I think I prefer the other option, of documenting that the latch clock pin pretty much behaves as a chip select. Having a separately described latch clock would mean no CS for these chips, and the SPI bindings and drivers don't expect devices without CS. -- jn
