On 23/12/2024 13:55, Michal Wilczynski wrote: > This patch introduces the reset controller driver for the T-HEAD Please do not use "This commit/patch/change", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 > TH1520 SoC. The controller manages hardware reset lines for various SoC > subsystems, such as the GPU. By exposing these resets via the Linux > reset subsystem, drivers can request and control hardware resets to > reliably initialize or recover key components. > > config RESET_TI_SCI > tristate "TI System Control Interface (TI-SCI) reset driver" > depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 677c4d1e2632..d6c2774407ae 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o > obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o > obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o > +obj-$(CONFIG_RESET_TH1520) += reset-th1520.o > obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o > obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o > obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o > diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c > new file mode 100644 > index 000000000000..10ca200690d5 > --- /dev/null > +++ b/drivers/reset/reset-th1520.c > @@ -0,0 +1,151 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2024 Samsung Electronics Co., Ltd. > + * Author: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx> > + */ > + > +#include <linux/of.h> This looks unused. What you need is mod_devicetable.h and MODULE_DEVICE_TABLE(th1520_reset_match) after th1520_reset_match. > +#include <linux/platform_device.h> > +#include <linux/reset-controller.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/reset/thead,th1520-reset.h> > + > + /* register offset in VOSYS_REGMAP */ > +#define TH1520_GPU_RST_CFG 0x0 > +#define TH1520_GPU_RST_CFG_MASK GENMASK(2, 0) > + > +/* register values */ > +#define TH1520_GPU_SW_GPU_RST BIT(0) > +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) > + > +struct th1520_reset_priv { > + struct reset_controller_dev rcdev; > + struct regmap *map; > +}; > + > +static inline struct th1520_reset_priv * > +to_th1520_reset(struct reset_controller_dev *rcdev) > +{ > + return container_of(rcdev, struct th1520_reset_priv, rcdev); > +} > + > +static void th1520_rst_gpu_enable(struct regmap *reg) > +{ > + int val; > + > + /* if the GPU is not in a reset state it, put it into one */ > + regmap_read(reg, TH1520_GPU_RST_CFG, &val); > + if (val) { Drop {} > + regmap_update_bits(reg, TH1520_GPU_RST_CFG, > + TH1520_GPU_RST_CFG_MASK, 0x0); > + } > + > + /* rst gpu clkgen */ > + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_CLKGEN_RST); > + > + /* > + * According to the hardware manual, a delay of at least 32 clock > + * cycles is required between de-asserting the clkgen reset and > + * de-asserting the GPU reset. Assuming a worst-case scenario with > + * a very high GPU clock frequency, a delay of 1 microsecond is > + * sufficient to ensure this requirement is met across all > + * feasible GPU clock speeds. > + */ > + udelay(1); > + > + /* rst gpu */ > + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_GPU_RST); > +} > + > +static void th1520_rst_gpu_disable(struct regmap *reg) > +{ > + regmap_update_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_RST_CFG_MASK, 0x0); > +} > + > +static int th1520_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); > + > + switch (id) { > + case TH1520_RESET_ID_GPU: > + th1520_rst_gpu_disable(priv->map); > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); > + > + switch (id) { > + case TH1520_RESET_ID_GPU: > + th1520_rst_gpu_enable(priv->map); > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct reset_control_ops th1520_reset_ops = { > + .assert = th1520_reset_assert, > + .deassert = th1520_reset_deassert, > +}; > + > +const struct regmap_config th1520_reset_regmap_config = { Should be static > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .fast_io = true, > +}; > + > +static int th1520_reset_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct th1520_reset_priv *priv; > + void __iomem *base; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + priv->map = > + devm_regmap_init_mmio(dev, base, &th1520_reset_regmap_config); Join lines. I feel you used some incorrect clang or other editor settings leading to such code format. Code can exceed 80 if improves readability, but if you wanted to wrap, then the wrapping should be after 'base' and next line aligned with opening (. > + if (IS_ERR(priv->map)) > + return PTR_ERR(priv->map); > + > + priv->rcdev.owner = THIS_MODULE; > + priv->rcdev.nr_resets = TH1520_RESET_NUM_IDS; > + priv->rcdev.ops = &th1520_reset_ops; Best regards, Krzysztof
