On Fri, Dec 20, 2024 at 02:39:13PM +0200, Ciprian Costea wrote:
Subject is wrong, this patch is not for common board
Simple said: "Add I2C[0..2] support for s32g2 and s32g3"
> From: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
>
> On both 'S32G2' and 'S32G3' SoCs there are five i2c controllers available
> (i2c0-i2c4). Specific S32G2/S32G3 based board 'i2c' dts device support
> will be added in further commits.
This commit have not touch "based board".
So"Add I2C[0..2] for S32G and S32G3 SoCs commit dts."
Allow only copy subject here for such simple add some nodes.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++
> 2 files changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..1a9683c234b7 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -333,6 +333,39 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401e4000 0x1000>;
reg should just after compatible.
Frank
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401e8000 0x1000>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401ec000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -341,6 +374,28 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x402d8000 0x1000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x402dc000 0x1000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..5d28b439906d 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -390,6 +390,42 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401e4000 0x1000>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401e8000 0x1000>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x401ec000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -398,6 +434,30 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x402d8000 0x1000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x402dc000 0x1000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
> --
> 2.45.2
>
