On Fri, Dec 06, 2024 at 10:11:25PM +0100, Christian Marangi wrote:
> Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU
> frequency scaling with SMC APIs and register a generic "cpufreq-dt"
> device.
>
> CPUFreq driver registers a get-only clock to get the current global CPU
> frequency from SMC and a Power Domain to configure the performance state
> for each OPP to apply the requested frequency from cpufreq-dt. This is
> needed as SMC use index instead of raw frequency.
>
> All CPU share the same frequency and can't be controlled independently.
> Current shared CPU frequency is returned by the related SMC command.
>
> Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq
> driver is needed with OPP v2 nodes declared in DTS.
>
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
[...]
> diff --git a/drivers/cpufreq/airoha-cpufreq.c b/drivers/cpufreq/airoha-cpufreq.c
> new file mode 100644
> index 000000000000..29738f61f401
> --- /dev/null
> +++ b/drivers/cpufreq/airoha-cpufreq.c
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/bitfield.h>
> +#include <linux/cpufreq.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +
> +#include "cpufreq-dt.h"
> +
[...]
> +
> +static unsigned long airoha_cpufreq_clk_get(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + const struct arm_smccc_1_2_regs args = {
> + .a0 = AIROHA_SIP_AVS_HANDLE,
> + .a1 = AIROHA_AVS_OP_GET_FREQ,
> + };
> + struct arm_smccc_1_2_regs res;
> +
> + arm_smccc_1_2_smc(&args, &res);
See below comment. Same applies here.
> +
> + /* SMCCC returns freq in MHz */
> + return res.a0 * 1000 * 1000;
> +}
> +
> +/* Airoha CPU clk SMCC is always enabled */
> +static int airoha_cpufreq_clk_is_enabled(struct clk_hw *hw)
> +{
> + return true;
> +}
> +
> +static const struct clk_ops airoha_cpufreq_clk_ops = {
> + .recalc_rate = airoha_cpufreq_clk_get,
> + .is_enabled = airoha_cpufreq_clk_is_enabled,
> + .round_rate = airoha_cpufreq_clk_round,
> +};
> +
> +static const char * const airoha_cpufreq_clk_names[] = { "cpu", NULL };
> +
> +/* NOP function to disable OPP from setting clock */
> +static int airoha_cpufreq_config_clks_nop(struct device *dev,
> + struct opp_table *opp_table,
> + struct dev_pm_opp *opp,
> + void *data, bool scaling_down)
> +{
> + return 0;
> +}
> +
> +static const char * const airoha_cpufreq_pd_names[] = { "perf" };
> +
> +static int airoha_cpufreq_set_performance_state(struct generic_pm_domain *domain,
> + unsigned int state)
> +{
> + const struct arm_smccc_1_2_regs args = {
> + .a0 = AIROHA_SIP_AVS_HANDLE,
> + .a1 = AIROHA_AVS_OP_FREQ_DYN_ADJ,
> + .a3 = state,
> + };
> + struct arm_smccc_1_2_regs res;
> +
> + arm_smccc_1_2_smc(&args, &res);
> +
I assume the compatible suggests SMCCCv1.2+ is implemented, but it is good
to check arm_smccc_get_version() and add build config dependency on
HAVE_ARM_SMCCC_DISCOVERY. Also use the SMCCC conduit and don't assume SMC.
--
Regards,
Sudeep
