The CMN PLL clock controller in Qualcomm IPQ chipsets provides the clocks to the networking hardware blocks that are internal or external to the SoC, and to the GCC. This driver configures the CMN PLL clock controller to enable the output clocks. The networking blocks include the internal blocks such as PPE (Packet Process Engine) and PCS blocks, and external hardware such as Ethernet PHY or switch. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. The controller expects the input reference clock from the internal Wi-Fi block acting as the clock source. The output clocks supplied by the controller are fixed rate clocks. The CMN PLL hardware block does not include any other function other than enabling the clocks to the networking hardware blocks and GCC. The driver is being enabled to support IPQ9574 SoC initially, and will be extended for other SoCs. Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> --- Changes in v7: - Update to use API regmap_set and clear_bits. - Update comment of CMN PLL reference clock to mention .xo could be 48 MHZ or 96 MHZ on different IPQ9574 RDP board. - Link to v6: https://lore.kernel.org/r/20241107-qcom_ipq_cmnpll-v6-0-a5cfe09de485@xxxxxxxxxxx Changes in v6: - Rename the reference clock of CMN PLL to ref_48mhz_clk. - Add the patch to update xo_board_clk to use fixed factor clock. - Link to v5: https://lore.kernel.org/r/20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@xxxxxxxxxxx Changes in v5: - Move the hardware configurations into set_rate() from determine_rate(). - Remove the dependency on IPQ_GCC_9574. - Correct the header files included. - Update reference clock of CMN PLL to use fixed factor clock. - Link to v4: https://lore.kernel.org/r/20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@xxxxxxxxxxx Changes in v4: - Rename driver file to ipq-cmn-pll.c - Register CMN PLL as a 12 GHZ clock. - Configure CMN PLL input ref clock using clk_ops::determine_rate(). Add the additional output clocks to GCC and PCS. - Update the same information in dtbindings. - Use PM clock APIs for input clock enablement. - Link to v3: https://lore.kernel.org/r/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@xxxxxxxxxxx Changes in v3: - Update description of dt-binding to explain scope of 'CMN' in CMN PLL. - Collect Reviewed-by tags for dtbindings and defconfig patches. - Enable PLL_LOCKED check for the stability of output clocks. - Link to v2: https://lore.kernel.org/r/20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@xxxxxxxxxxx Changes in v2: - Rename the dt-binding file with the compatible. - Remove property 'clock-output-names' from dt-bindings and define names in the driver. Add qcom,ipq-cmn-pll.h to export the output clock specifier. - Alphanumeric ordering of 'cmn_pll_ref_clk' node in DTS. - Fix allmodconfig error reported by test robot. - Replace usage of "common" to "CMN" to match the name with the hardware specification. - Clarify in commit message on scope of CMN PLL function. - Link to v1: https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@xxxxxxxxxxx --- Luo Jie (5): dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC clk: qcom: Add CMN PLL clock controller driver for IPQ SoC arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC arm64: dts: qcom: Update IPQ9574 xo_board_clk to use fixed factor clock .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 85 ++++ arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 24 +- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +- arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++ 8 files changed, 601 insertions(+), 3 deletions(-) --- base-commit: e25c8d66f6786300b680866c0e0139981273feba change-id: 20241216-qcom_ipq_cmnpll-f5c84724db9d Best regards, -- Luo Jie <quic_luoj@xxxxxxxxxxx>
