On 14/12/2024 10:12, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> Introduce Morello SoC dts.
>
> So Morello is an architecture, not a board or platform? You cannot have
> both...
>
>
So, Morello is an architecture an SoC and a platform.
To distinguish them I propose:
- arm,morello for # the SoC
- arm,morello-sdp # for the platform.
sdp: Software Development Platform.
>
>
>>
>> Cc: Sudeep Holla <sudeep.holla@xxxxxxx>
>> Cc: Rob Herring <robh@xxxxxxxxxx>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@xxxxxxx>
>> ---
>> arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++
>> 1 file changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts
>>
>> diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts
>> new file mode 100644
>> index 000000000000..3c5247121e4d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/arm/morello-soc.dts
>> @@ -0,0 +1,267 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
>> +/*
>> + * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
>> +
>> + */
>> +
>> +/dts-v1/;
>> +#include "morello.dtsi"
>> +
>> +/ {
>> + model = "Arm Morello System Development Platform";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + secure-firmware@ff000000 {
>> + reg = <0 0xff000000 0 0x01000000>;
>> + no-map;
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> + cpu0: cpu0@0 {
>> + compatible = "arm,neoverse-n1";
>> + reg = <0x0 0x0>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + clocks = <&scmi_dvfs 0>;
>> + };
>> + cpu1: cpu1@100 {
>> + compatible = "arm,neoverse-n1";
>> + reg = <0x0 0x100>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + clocks = <&scmi_dvfs 0>;
>> + };
>> + cpu2: cpu2@10000 {
>> + compatible = "arm,neoverse-n1";
>> + reg = <0x0 0x10000>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + clocks = <&scmi_dvfs 1>;
>> + };
>> + cpu3: cpu3@10100 {
>> + compatible = "arm,neoverse-n1";
>> + reg = <0x0 0x10100>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + clocks = <&scmi_dvfs 1>;
>> + };
>> + };
>> +
>> + /* The first bank of memory, memory map is actually provided by UEFI. */
>> + memory@80000000 {
>> + device_type = "memory";
>> + /* [0x80000000-0xffffffff] */
>> + reg = <0x00000000 0x80000000 0x0 0x7F000000>;
>> + };
>> +
>> + memory@8080000000 {
>> + device_type = "memory";
>> + /* [0x8080000000-0x83f7ffffff] */
>> + reg = <0x00000080 0x80000000 0x3 0x78000000>;
>> + };
>> +
>> + smmu_pcie: iommu@4f400000 {
>
> This all is weird. MMIO nodes outside of soc, soc pieces defined in DTS
> instead of DTSI.
>
> Please look first how all other DTS and DTSI are done. Also carefully
> read DTS coding style.
>
>
All right, will do.
>
> Best regards,
> Krzysztof
--
Regards,
Vincenzo
