Hi Tudor, On Tue, 17 Dec 2024 at 09:40, Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote: > > The Samsung Exynos mailbox controller has 16 flag bits for hardware > interrupt generation and a shared register for passing mailbox messages. > When the controller is used by the ACPM protocol the shared register is > ignored and the mailbox controller acts as a doorbell. The controller > just raises the interrupt to APM after the ACPM protocol has written > the message to SRAM. > > Add support for the Samsung Exynos mailbox controller. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> > --- Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx> regards, Peter [..]
