Hi Laurent
On Wed, Dec 18, 2024 at 01:46:22AM +0200, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Tue, Dec 17, 2024 at 06:53:14PM +0100, Jacopo Mondi wrote:
> > Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.
> >
> > Signed-off-by: Jacopo Mondi <jacopo.mondi@xxxxxxxxxxxxxxxx>
> > ---
> > drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > index 55c8dd032fc325c63727f21dc4d38b8e08ce0ca0..dc9ac2839ad9bb6c222db015de72fe8d9e7fe208 100644
> > --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > @@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> > DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
> > DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
> > DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
> > + DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D4_VIO),
> > + DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D4_VIO),
>
> I can't really validate the parent as the documentation lists multiple
> S0 clocks that driver the FCP, but this is one of them, so
Here I decided to use the same clock as the VINs (200MHz)
However the ISPs clock parent is set to R8A779G0_CLK_S0D2_VIO (400MHz)
but that does not support the VSPX.
The only clock parent that can feed [FCPVX, VSPX and ISP] is the
800MHz R8A779G0_CLK_S0D1_VIO parent.
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
>
> I expect that in reality the MSTP bit gates multiple clocks.
>
> > DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
> > DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
> > DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
>
> --
> Regards,
>
> Laurent Pinchart
