Add documentation for the pin controller found on the Renesas RZ/G3E
(R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more
pins(P00-PS3).
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v3->v4:
* Dropped ack tag from Conor as there is separate file for RZG3E_P*
definitions
v2->v3:
* Updated the macros with hardware indices in the hardware manual.
* The changes are trivial, so retained ack tag from Conor.
v1->v2:
* Fixed the warnings reported by bot.
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 7 +++-
.../pinctrl/renesas,r9a09g047-pinctrl.h | 41 +++++++++++++++++++
2 files changed, 46 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index a1805b6e3f63..768bb3c2b456 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@@ -125,7 +126,7 @@ additionalProperties:
drive-push-pull: true
renesas,output-impedance:
description:
- Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+ Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
property corresponds to register bit values that can be set in the PFC_IOLH_mn
register, which adjusts the drive strength value and is pin-dependent.
$ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a09g057-pinctrl
+ enum:
+ - renesas,r9a09g047-pinctrl
+ - renesas,r9a09g057-pinctrl
then:
properties:
resets:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
new file mode 100644
index 000000000000..b2cda1a44b0a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_RZG3E_PINCTRL_H
+#define __DT_BINDINGS_RZG3E_PINCTRL_H
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
+#define RZG3E_P0 0
+#define RZG3E_P1 1
+#define RZG3E_P2 2
+#define RZG3E_P3 3
+#define RZG3E_P4 4
+#define RZG3E_P5 5
+#define RZG3E_P6 6
+#define RZG3E_P7 7
+#define RZG3E_P8 8
+#define RZG3E_PA 10
+#define RZG3E_PB 11
+#define RZG3E_PC 12
+#define RZG3E_PD 13
+#define RZG3E_PE 14
+#define RZG3E_PF 15
+#define RZG3E_PG 16
+#define RZG3E_PH 17
+#define RZG3E_PJ 19
+#define RZG3E_PK 20
+#define RZG3E_PL 21
+#define RZG3E_PM 22
+#define RZG3E_PS 28
+
+#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
+#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
+
+#endif /* __DT_BINDINGS_RZG3E_PINCTRL_H */
--
2.43.0
