Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> --- .../mailbox/riscv,rpmi-shmem-mbox.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml new file mode 100644 index 000000000000..8d713ba7ffc7 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,sbi-mpxy-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox + +maintainers: + - Anup Patel <anup@xxxxxxxxxxxxxx> + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a common shared + memory based RPMI transport. This RPMI shared memory transport integrates as + mailbox controller in the SBI implementation or supervisor software whereas + each RPMI service group is mailbox client in the SBI implementation and + supervisor software. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,rpmi-shmem-mbox + + reg: + oneOf: + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - description: A2P doorbell address + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: A2P doorbell address + + reg-names: + oneOf: + - items: + - const: a2p-req + - const: p2a-ack + - const: p2a-req + - const: a2p-ack + - const: db-reg + - items: + - const: a2p-req + - const: p2a-ack + - const: db-reg + + interrupts: + minItems: 1 + maxItems: 1 + description: + The RPMI shared memory transport supports wired interrupt specified by + this property as the P2A doorbell. + + msi-parent: + description: + The RPMI shared memory transport supports MSI as P2A doorbell and this + property specifies the target MSI controller. + + riscv,slot-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + description: + Power-of-2 RPMI slot size of the RPMI shared memory transport. + + riscv,db-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Update only the register bits of doorbell defined by the mask (32 bit). + If this property is not present then mask is assumed to be 0xffffffff. + + riscv,db-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value written to the doorbell register bits (32-bit access) specified + by the riscv,db-mask property. If this property is not present then + value is assumed to be 0x1. + + "#mbox-cells": + const: 1 + description: + The first cell specifies RPMI service group ID. + +required: + - compatible + - reg + - reg-names + - riscv,slot-size + - "#mbox-cells" + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + // Example 1 (RPMI shared memory with only 2 queues): + mailbox@10080000 { + compatible = "riscv,rpmi-shmem-mbox"; + reg = <0x00 0x10080000 0x00 0x10000>, + <0x00 0x10090000 0x00 0x10000>, + <0x00 0x100a0000 0x00 0x4>; + reg-names = "a2p-req", "p2a-ack", "db-reg"; + msi-parent = <&imsic_mlevel>; + riscv,slot-size = <64>; + #mbox-cells = <1>; + }; + - | + // Example 2 (RPMI shared memory with only 4 queues): + mailbox@10001000 { + compatible = "riscv,rpmi-shmem-mbox"; + reg = <0x00 0x10001000 0x00 0x800>, + <0x00 0x10001800 0x00 0x800>, + <0x00 0x10002000 0x00 0x800>, + <0x00 0x10002800 0x00 0x800>, + <0x00 0x10003000 0x00 0x4>; + reg-names = "a2p-req", "p2a-ack", "db-reg"; + msi-parent = <&imsic_mlevel>; + riscv,slot-size = <64>; + riscv,db-mask = <0x00008000>; + riscv,db-value = <0x00008000>; + #mbox-cells = <1>; + }; -- 2.43.0
