On Tue, Nov 26, 2024 at 10:21 AM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system
> controller that need to be de-asserted/asserted when power is turned
> on/off. This signal, called PWRRDY, is controlled through a specific
> register in the system controller memory space.
>
> Add the renesas,sysc-signal DT property to describe the relation b/w the
> system controller and the USB PHY on the Renesas RZ/G3S. This property
> provides a phandle to the system controller, along with the offset within
> the system controller memory space that manages the signal and a bitmask
> that indicates the specific bits required to control the signal.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
