On 12/5/2024 8:31 PM, Neil Armstrong wrote:
> Each GPU OPP requires a specific peak DDR bandwidth, let's add
> those to each OPP and also the related interconnect path.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
I haven't checked each bw value, still
Reviewed-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
-Akhil
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..955f58b2cb4e4ca3fd33f1555e36a15cfc82d642 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -14,6 +14,7 @@
> #include <dt-bindings/firmware/qcom,scm.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -2114,6 +2115,10 @@ gpu: gpu@3d00000 {
> qcom,gmu = <&gmu>;
> #cooling-cells = <2>;
>
> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> +
> status = "disabled";
>
> zap-shader {
> @@ -2127,41 +2132,49 @@ gpu_opp_table: opp-table {
> opp-680000000 {
> opp-hz = /bits/ 64 <680000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <16500000>;
> };
>
> opp-615000000 {
> opp-hz = /bits/ 64 <615000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
> + opp-peak-kBps = <16500000>;
> };
>
> opp-550000000 {
> opp-hz = /bits/ 64 <550000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <12449218>;
> };
>
> opp-475000000 {
> opp-hz = /bits/ 64 <475000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
> + opp-peak-kBps = <8171875>;
> };
>
> opp-401000000 {
> opp-hz = /bits/ 64 <401000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <6671875>;
> };
>
> opp-348000000 {
> opp-hz = /bits/ 64 <348000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
> + opp-peak-kBps = <6074218>;
> };
>
> opp-295000000 {
> opp-hz = /bits/ 64 <295000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> + opp-peak-kBps = <6074218>;
> };
>
> opp-220000000 {
> opp-hz = /bits/ 64 <220000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
> + opp-peak-kBps = <6074218>;
> };
> };
> };
>
