Add documentation for the pin controller found on the Renesas RZ/G3E
(R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more
pins(P00-PS3). The port number is alpha-numeric compared to the number on
the other SoCs. So add macros for alpha-numeric to number conversion.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 4 ++-
include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 25 +++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index a1805b6e3f63..499b1a6a8af6 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@@ -125,7 +126,7 @@ additionalProperties:
drive-push-pull: true
renesas,output-impedance:
description:
- Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+ Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
property corresponds to register bit values that can be set in the PFC_IOLH_mn
register, which adjusts the drive strength value and is pin-dependent.
$ref: /schemas/types.yaml#/definitions/uint32
@@ -142,6 +143,7 @@ allOf:
properties:
compatible:
contains:
+ const: renesas,r9a09g047-pinctrl
const: renesas,r9a09g057-pinctrl
then:
properties:
diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
index c78ed5e5efb7..1b1b1114a84c 100644
--- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
+++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
@@ -11,13 +11,38 @@
#define RZG2L_PINS_PER_PORT 8
+#define RZG3E_P0 0
+#define RZG3E_P1 1
+#define RZG3E_P2 2
+#define RZG3E_P3 3
+#define RZG3E_P4 4
+#define RZG3E_P5 5
+#define RZG3E_P6 6
+#define RZG3E_P7 7
+#define RZG3E_P8 8
+#define RZG3E_PA 9
+#define RZG3E_PB 10
+#define RZG3E_PC 11
+#define RZG3E_PD 12
+#define RZG3E_PE 13
+#define RZG3E_PF 14
+#define RZG3E_PG 15
+#define RZG3E_PH 16
+#define RZG3E_PJ 17
+#define RZG3E_PK 18
+#define RZG3E_PL 19
+#define RZG3E_PM 20
+#define RZG3E_PS 21
+
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
+#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
/* Convert a port and pin label to its global pin index */
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
+#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */
--
2.43.0
