On Thu, Dec 5, 2024 at 2:33 AM Peter Geis <pgwipeout@xxxxxxxxx> wrote: > > > > Cycling through the rx_delay range on two boards shows that is a large > > > > "good" region from 0x11 to 0x35 (see below for details). > > > > > > > > > > Is this missing a "there" after that? "that there is a large good region"? > > That large good region is actually an eye that you are aligning to the > clock signal. The board is on the tail end of the eye where it is > barely working. This value is supposed to be tuned to be in the middle > of that eye. You may want to test the old boards against the new > boards, because if the original board was tuned correctly something > may have changed in hardware that caused a significant shift in the > eye location. Examples of this would be changing to a new phy, > enabling phy delays, or changes in the trace length. If this is the > case, you'll probably want to make a new variant of the dts to cover > this. Thanks for the comment. Nothing should have changed on the board, and I dug out a really old one to verify. It behaves the same. 0x10 seems to be the lower edge of things still working. I will put rx_delay in the center of the eye with the v3 patch. I also checked tx_delay, and we already seem to be in the middle of the eye, so I won't touch it. Best regards, Jakob
