The Agilex5 SoCs have three Synopsys DWXGMAC-compatible ethernet
IP-cores.
Add a SoC-specific front compatible to the binding.
Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/net/socfpga-dwmac.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml
index 022d9eb7011d47666b140aaecf54541ca3dec0ec..c578b4280c6c85f08b6e0918352d38ed98998489 100644
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml
@@ -21,6 +21,7 @@ select:
enum:
- altr,socfpga-stmmac # For Cyclone5/Arria5 SoCs
- altr,socfpga-stmmac-a10-s10 # For Arria10/Agilex/Stratix10 SoCs
+ - altr,socfpga-stmmac-agilex5 # For Agilex5 SoCs
required:
- compatible
@@ -44,6 +45,12 @@ properties:
- altr,socfpga-stmmac-a10-s10
- const: snps,dwmac-3.74a
- const: snps,dwmac
+ - items:
+ - enum:
+ - altr,socfpga-stmmac-agilex5
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwxgmac-2.10
+ - const: snps,dwxgmac
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
--
2.46.0
