Quoting Krzysztof Kozlowski (2024-11-28 07:08:00)
> @@ -360,13 +384,14 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
> u32 val;
> int count;
> int ret;
> - const char *name = clk_hw_get_name(&pll->clkr.hw);
> + const char *name;
>
> ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
> if (ret)
> return ret;
>
> - for (count = 200; count > 0; count--) {
> + /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */
> + for (count = 1500; count > 0; count--) {
> ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
> if (ret)
> return ret;
> @@ -378,6 +403,13 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
> udelay(1);
> }
>
> + /* Called with clocks already registered ... */
> + if (pll->clkr.hw.core)
> + name = clk_hw_get_name(&pll->clkr.hw);
> + else
> + /* or before registering, when init data is present */
> + name = pll->clkr.hw.init->name;
This is sad. Why can't we enable the PLL from the clk prepare/enable
path? PLLs are typically calibrated during clk_prepare().
> +
> WARN(1, "%s failed to %s!\n", name, action);
> return -ETIMEDOUT;
> }
> @@ -2524,6 +2556,129 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
>
> +static int alpha_pll_pongo_elu_enable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + int ret;
> +
> + /* Check if PLL is already enabled */
> + if (trion_pll_is_enabled(pll, regmap))
> + return 0;
> +
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> + if (ret)
> + return ret;
> +
> + /* Set operation mode to RUN */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> +
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Enable the global PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
> + if (ret)
> + return ret;
> +
> + /* Ensure that the write above goes through before returning. */
> + mb();
> +
> + return ret;
> +}
> +
> +static void alpha_pll_pongo_elu_disable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + int ret;
> +
> + /* Disable the global PLL output */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> + if (ret)
> + return;
> +
> + /* Place the PLL mode in STANDBY */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +}
> +
> +static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 l;
> +
> + if (regmap_read(regmap, PLL_L_VAL(pll), &l))
> + return 0;
> +
> + l &= PONGO_PLL_L_VAL_MASK;
> +
> + return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll));
> +}
> +
> +const struct clk_ops clk_alpha_pll_pongo_elu_ops = {
> + .enable = alpha_pll_pongo_elu_enable,
> + .disable = alpha_pll_pongo_elu_disable,
> + .recalc_rate = alpha_pll_pongo_elu_recalc_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_pongo_elu_ops);
GPL please.
> +
> +void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll,
> + struct regmap *regmap,
> + const struct alpha_pll_config *config)
> +{
> + u32 val;
> +
> + regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK,
> + PONGO_PLL_OUT_MASK);
> +
> + if (trion_pll_is_enabled(pll, regmap))
> + return;
> +
> + if (regmap_read(regmap, PLL_L_VAL(pll), &val))
> + return;
> + val &= PONGO_PLL_L_VAL_MASK;
> + if (val)
> + return;
> +
> + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
> + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val);
> + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
> + config->user_ctl_val | PONGO_PLL_OUT_MASK);
> + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val);
> +
> + /* Disable PLL output */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Enable PLL intially to one-time calibrate against XO. */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> + regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT);
> +
> + /* Set regmap for wait_for_pll() */
> + pll->clkr.regmap = regmap;
> + if (wait_for_pll_enable_lock(pll))
> + return;
> +
> + /* Disable PLL after one-time calibration. */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +
> + /* Select internally generated clock. */
> + regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, PONGO_CLOCK_SELECT);
> +}
> +EXPORT_SYMBOL(clk_pongo_elu_pll_configure);
GPL please.
