From: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
S32G2 and S32G3 SoCs share the FlexCAN module with i.MX SoCs, with some
hardware integration particularities.
Main difference covered by this patchset relates to interrupt management.
On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, MBs 0-7 and MBs 8-127 respectively.
Changes in V3:
- Added Vincent Mailhol's Reviewed-by tag on the second patch
- Changed to 'platform_get_irq_byname' for second range of mailboxes
- Made several rephasing in bindings doc
- Removed Frank Li's Reviewed-by tags since changes were made afterwards.
Changes in V2:
- Separated 'FLEXCAN_QUIRK_NR_IRQ_3' quirk addition from S32G SoC Flexcan
support.
- Provided more information in dt-bindings documentation with respect to
FlexCAN module integration on S32G SoCs.
- Fixed and irq resource freeing management issue.
Ciprian Marian Costea (3):
dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support
can: flexcan: Add quirk to handle separate interrupt lines for
mailboxes
can: flexcan: add NXP S32G2/S32G3 SoC support
.../bindings/net/can/fsl,flexcan.yaml | 46 +++++++++++++++++--
drivers/net/can/flexcan/flexcan-core.c | 35 +++++++++++++-
drivers/net/can/flexcan/flexcan.h | 5 ++
3 files changed, 81 insertions(+), 5 deletions(-)
--
2.45.2
