Hi I was working on some scenarios where I have multi-threading on for my ARM CPUs and would like to share L1 caches between two hyperthreaded cores. This is particularly possible to be expressed via ACPI PPTT tables, and it is important to be able to express the same thing on both devicetree and ACPI PPTT because some use device tree and some use PPTT table for topology and sharing purposes on ARM. Currently L1 caches are expressed via some properties within CPU object and it seems not possible to use a separate cache object for L1 looking at the latest spec. I wonder what the thought are on this? Thanks, Alireza
