On Thu, Nov 28, 2024 at 04:10:53PM +0800, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, board related gpios,
> PMIC regulators, etc.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 ++++++++++++++++++++++-
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> index 7eed19a694c3..7f97f771c44a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
> &gcc {
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&sleep_clk>,
> - <0>,
> + <&pcie0_phy>,
Review comment was ignored, NAK.
> <0>,
> <0>,
> <0>,
> @@ -223,6 +223,23 @@ &gcc {
> <0>;
> };
>
> +&pcie0 {
> + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l6a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
> @@ -247,6 +264,31 @@ &rpmhcc {
> clock-names = "xo";
> };
>
> +&tlmm {
> + pcie0_default_state: pcie0-default-state {
> + clkreq-pins {
> + pins = "gpio1";
> + function = "pcie0_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-pins {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-pins {
> + pins = "gpio0";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> &uart7 {
> status = "okay";
> };
> --
> 2.34.1
>
--
With best wishes
Dmitry
