Hi Heiko, On 2024-11-17 21:18, Heiko Stuebner wrote: > As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72 > cores, four Cortex-A53 cores and Mali-G52 MC3 GPU. > > Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to > use UFS 2.0 storage. > > Video Output options are a HDMI port, a DSI connector as well as Display- > Port via the TypeC connector (all of them not yet supported). > > Networking options are a Low-profile Gigabit Ethernet RJ45 port with > Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module. > > USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C > and it comes with 40-pin GPIO header > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> > --- > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 745 ++++++++++++++++++ > 2 files changed, 746 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index ac7574bfbf94..3562d6e64b2e 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-roc-pc.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts > new file mode 100644 > index 000000000000..75ee18ef3817 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts [snip] > +&gmac0 { > + /* Use rgmii-rxid mode to disable rx delay inside Soc */ > + phy-mode = "rgmii-rxid"; > + clock_in_out = "output"; > + > + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; > + snps,reset-active-low; > + /* Reset time is 20ms, 100ms for rtl8211f */ > + snps,reset-delays-us = <0 20000 100000>; The snps,reset- props are deprecated, reset- props should probably be added to the rgmii_phy0 node. > + > + pinctrl-names = "default"; > + pinctrl-0 = <ð0m0_miim > + ð0m0_tx_bus2 > + ð0m0_rx_bus2 > + ð0m0_rgmii_clk > + ð0m0_rgmii_bus > + ðm0_clk0_25m_out>; > + > + tx_delay = <0x21>; > + /* rx_delay = <0x3f>; */ > + > + phy-handle = <&rgmii_phy0>; > + status = "okay"; > +}; > + > +&mdio0 { > + status = "okay"; > + > + rgmii_phy0: phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; This could possible be changed to ethernet-phy-id001c.c916 if moving reset- props cause Ethernet phy detection issues and phy was not reset by bootloader. Regards, Jonas > + reg = <0x1>; > + clocks = <&cru REFCLKO25M_GMAC0_OUT>; > + }; > +}; > + [snip]