On 20.11.2024 12:47:02, Ciprian Marian Costea wrote: > > > > > The mainline driver already handles the 2nd mailbox range (same > > > > > 'flexcan_irq') is used. The only difference is that for the 2nd mailbox > > > > > range a separate interrupt line is used. > > > > > > > > AFAICS the IP core supports up to 128 mailboxes, though the driver only > > > > supports 64 mailboxes. Which mailboxes do you mean by the "2nd mailbox > > > > range"? What about mailboxes 64..127, which IRQ will them? > > > > > > On S32G the following is the mapping between FlexCAN IRQs and mailboxes: > > > - IRQ line X -> Mailboxes 0-7 > > > - IRQ line Y -> Mailboxes 8-127 (Logical OR of Message Buffer Interrupt > > > lines 127 to 8) > > > > > > By 2nd range, I was refering to Mailboxes 8-127. > > > > Interesting, do you know why it's not symmetrical (0...63, 64...127)? > > Can you point me to the documentation. > > Unfortunately I do not know why such hardware integration decisions have > been made. > > Documentation for S32G3 SoC can be found on the official NXP website, > here: > https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g3-processors-for-vehicle-networking:S32G3 > > But please note that you need to setup an account beforehand. I have that already, where is the mailbox to IRQ mapping described? regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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