On Tue, Nov 19, 2024 at 10:10:52AM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
>
> Add device type data for S32G2/S32G3 SoC.
>
> FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
> management is different. This initial S32G2/S32G3 SoC FlexCAN support
> paves the road to address such differences.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> drivers/net/can/flexcan/flexcan-core.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
> index ac1a860986df..f0dee04800d3 100644
> --- a/drivers/net/can/flexcan/flexcan-core.c
> +++ b/drivers/net/can/flexcan/flexcan-core.c
> @@ -386,6 +386,15 @@ static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
> FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
> };
>
> +static const struct flexcan_devtype_data nxp_s32g2_devtype_data = {
> + .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> + FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
> + FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
> + FLEXCAN_QUIRK_SUPPORT_ECC |
> + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
> + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
> +};
> +
> static const struct can_bittiming_const flexcan_bittiming_const = {
> .name = DRV_NAME,
> .tseg1_min = 4,
> @@ -2041,6 +2050,7 @@ static const struct of_device_id flexcan_of_match[] = {
> { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
> { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
> { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
> + { .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, },
> { /* sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, flexcan_of_match);
> --
> 2.45.2
>
