On Tue, Nov 05, 2024 at 06:35:12PM +0000, Valentina Fernandez wrote: > Add a dt-binding for the Microchip Inter-Processor Communication (IPC) > mailbox controller. > > Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@xxxxxxxxxxxxx> > --- > .../bindings/mailbox/microchip,sbi-ipc.yaml | 117 ++++++++++++++++++ > 1 file changed, 117 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > new file mode 100644 > index 000000000000..9e67c09e4bea > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > @@ -0,0 +1,117 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Inter-processor communication (IPC) mailbox controller > + > +maintainers: > + - Valentina Fernandez <valentina.fernandezalanis@xxxxxxxxxxxxx> > + > +description: > + The Microchip Inter-processor Communication (IPC) facilitates > + message passing between processors using an interrupt signaling > + mechanism. > + > +properties: > + compatible: > + oneOf: > + - description: > + Intended for use by software running in supervisor privileged > + mode (s-mode). This SBI interface is compatible with the Mi-V > + Inter-hart Communication (IHC) IP. > + items: > + - const: microchip,sbi-ipc > + > + - description: > + SoC-specific compatible, intended for use by the SBI > + implementation in machine mode (m-mode). > + items: > + - const: microchip,miv-ihc-rtl-v2 Usually SoC specific compatibles don't have version numbers. And all hardware in an SoC is RTL at some point. So microchip,miv-ihc should be sufficient if 'miv' is an SoC. > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 5 > + > + interrupt-names: > + minItems: 1 > + maxItems: 5 > + items: > + pattern: "^hart-[0-5]+$" > + > + "#mbox-cells": > + description: > > + For the SBI "device", the cell represents the global "logical" channel IDs. > + The meaning of channel IDs are platform firmware dependent. > + > + For the SoC-specific compatible string, the cell represents the physical > + channel and does not vary based on the platform firmware. > + const: 1 > + > + microchip,ihc-chan-disabled-mask: > + description: > > + Represents the enable/disable state of the bi-directional IHC > + channels within the MIV-IHC IP configuration. > + > + The mask is a 16-bit value, but only the first 15 bits are utilized. > + Each of the bits corresponds to one of the 15 IHC channels. That can be expressed as a constraint: maximum: 0x7fff Then you can drop this paragraph. > + > + A bit set to '1' indicates that the corresponding channel is disabled, > + and any read or write operations to that channel will return zero. > + > + A bit set to '0' indicates that the corresponding channel is enabled > + and will be accessible through its dedicated address range registers. > + > + The remaining bit of the 16-bit mask is reserved and should be ignored. And drop this one. > + > + The actual enable/disable state of each channel is determined by the > + IP block’s configuration. > + $ref: /schemas/types.yaml#/definitions/uint16 > + default: 0 > + > +required: > + - compatible > + - interrupts > + - interrupt-names > + - "#mbox-cells" > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: microchip,sbi-ipc > + then: > + properties: > + reg: false > + microchip,ihc-chan-disabled-mask: false > + else: > + required: > + - reg > + - microchip,ihc-chan-disabled-mask > + > +examples: > + - | > + mailbox { > + compatible = "microchip,sbi-ipc"; > + interrupt-parent = <&plic>; > + interrupts = <180>, <179>, <178>; > + interrupt-names = "hart-1", "hart-2", "hart-3"; > + #mbox-cells = <1>; > + }; > + - | > + mailbox@50000000 { > + compatible = "microchip,miv-ihc-rtl-v2"; > + microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; > + reg = <0x50000000 0x1C000>; > + interrupt-parent = <&plic>; > + interrupts = <180>, <179>, <178>; > + interrupt-names = "hart-1", "hart-2", "hart-3"; > + #mbox-cells = <1>; > + }; > -- > 2.34.1 >
