by schematic[1], pcie2x1l2 CLKREQ and WAKE pins are connected. describe them in dts. [1] https://dl.radxa.com/rock5/5c/docs/hw/v1100/radxa_rock_5c_schematic_v1100.pdf Fixes: 3ddf5cdb77e6 ("arm64: dts: rockchip: add Radxa ROCK 5C") Signed-off-by: FUKAUMI Naoki <naoki@xxxxxxxxx> --- Changes in v3: - none Changes in v2: - reword commit message --- arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index 9b14d5383cdc..997e95bb5b74 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -419,7 +419,9 @@ rgmii_phy1: ethernet-phy@1 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie20x1_2_perstn_m0>; + pinctrl-0 = <&pcie20x1_2_perstn_m0>, + <&pcie20x1m0_clkreqn>, + <&pcie20x1m0_waken>; reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&pcie2x1l2_3v3>; status = "okay"; -- 2.43.0
