Add the documentation for VOP2 video ports reset clocks.
One reset can be set per video port.
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Signed-off-by: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
---
.../display/rockchip/rockchip-vop2.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
index 2531726af306b..5b59d91de47bd 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -65,6 +65,26 @@ properties:
- const: dclk_vp3
- const: pclk_vop
+ resets:
+ minItems: 5
+ items:
+ - description: AXI clock reset.
+ - description: AHB clock reset.
+ - description: Pixel clock reset for video port 0.
+ - description: Pixel clock reset for video port 1.
+ - description: Pixel clock reset for video port 2.
+ - description: Pixel clock reset for video port 3.
+
+ reset-names:
+ minItems: 5
+ items:
+ - const: aclk
+ - const: hclk
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+ - const: dclk_vp3
+
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -128,6 +148,11 @@ allOf:
clock-names:
minItems: 7
+ resets:
+ minItems: 6
+ reset-names:
+ minItems: 6
+
ports:
required:
- port@0
@@ -152,6 +177,11 @@ allOf:
clock-names:
maxItems: 5
+ resets:
+ maxItems: 5
+ reset-names:
+ maxItems: 5
+
ports:
required:
- port@0
@@ -183,6 +213,16 @@ examples:
"dclk_vp0",
"dclk_vp1",
"dclk_vp2";
+ resets = <&cru SRST_A_VOP>,
+ <&cru SRST_H_VOP>,
+ <&cru SRST_VOP0>,
+ <&cru SRST_VOP1>,
+ <&cru SRST_VOP2>;
+ reset-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
power-domains = <&power RK3568_PD_VO>;
iommus = <&vop_mmu>;
vop_out: ports {
--
2.47.0
