Update the relavent DT bindings for PCIe, add new config to the phy driver add pcie and phy nodes to the .dtsi file and enable then in board .dts file for the qcs8300-ride platform. build dependencies: -devicetree: https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@xxxxxxxxxxx/ - tlmm: https://lore.kernel.org/linux-arm-msm/20240819064933.1778204-1-quic_jingyw@xxxxxxxxxxx/ - gcc: https://lore.kernel.org/all/20240822-qcs8300-gcc-v2-0-b310dfa70ad8@xxxxxxxxxxx/ - interconnect: https://lore.kernel.org/linux-arm-msm/20240910101013.3020-1-quic_rlaggysh@xxxxxxxxxxx/ Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> --- Have follwing changes: - Document the QMP PCIe PHY on the QCS8300 platform. - Add dedicated schema for the PCIe controllers found on QCS8300. - Add compatible for qcs8300 platform. - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Ziyue Zhang (5): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 arm64: dts: qcom: qcs8300: enable pcie1 for QCS8300 .../bindings/pci/qcom,pcie-sa8775p.yaml | 7 +- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 86 ++++- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 355 ++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 +++++ 5 files changed, 536 insertions(+), 3 deletions(-) base-commit: eb6a0b56032c62351a59a12915a89428bce68d1d -- 2.34.1
