Same to "ldb" clock rate validation, call clk_round_rate() to validate "pix"(pixel clock) rate too. This may filter modes out whose pixel clock rates cannot be supported by the pixel clock tree. For example, when the pixel clock is derived from the i.MX8MP video_pll1_out clock and video_pll1_out clock rate is 1.0395GHz, mode 720x576p@50Hz with 27MHz pixel clock rate will be filtered out in LDB split mode because the PLL clock rate does satisfy the "ldb" clock rate(27MHz * 3.5 = 94.5MHz) with 11 division ratio while it cannot satisfy the "pix" clock rate with 38.5 division ratio(only integer division ratio is supported). Signed-off-by: Liu Ying <victor.liu@xxxxxxx> --- Note that this patch depends on a patch in shawnguo/imx/fixes: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241017031146.157996-1-marex@xxxxxxx/ Also, this patch depends on patch 2. v7: * Put pixel clock properly by adding a dev managed action in fsl_ldb_probe(). v6: * New patch. drivers/gpu/drm/bridge/fsl-ldb.c | 53 +++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index d9436ff9ccc3..9afd91c30c88 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -4,6 +4,7 @@ */ #include <linux/clk.h> +#include <linux/device.h> #include <linux/media-bus-format.h> #include <linux/mfd/syscon.h> #include <linux/module.h> @@ -11,6 +12,7 @@ #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/units.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_bridge.h> @@ -86,7 +88,8 @@ struct fsl_ldb { struct device *dev; struct drm_bridge bridge; struct drm_bridge *next_bridge; - struct clk *clk; + struct clk *clk_ldb; + struct clk *clk_pixel; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; bool ch0_enabled; @@ -176,15 +179,15 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, mode = &crtc_state->adjusted_mode; requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - clk_set_rate(fsl_ldb->clk, requested_link_freq); + clk_set_rate(fsl_ldb->clk_ldb, requested_link_freq); - configured_link_freq = clk_get_rate(fsl_ldb->clk); + configured_link_freq = clk_get_rate(fsl_ldb->clk_ldb); if (configured_link_freq != requested_link_freq) dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", configured_link_freq, requested_link_freq); - clk_prepare_enable(fsl_ldb->clk); + clk_prepare_enable(fsl_ldb->clk_ldb); /* Program LDB_CTRL */ reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | @@ -237,7 +240,7 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); - clk_disable_unprepare(fsl_ldb->clk); + clk_disable_unprepare(fsl_ldb->clk_ldb); } #define MAX_INPUT_SEL_FORMATS 1 @@ -269,15 +272,21 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { + unsigned long link_freq, pclk_rate, rounded_pclk_rate; struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - unsigned long link_freq; if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) return MODE_CLOCK_HIGH; /* Validate "ldb" clock rate. */ link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - if (link_freq != clk_round_rate(fsl_ldb->clk, link_freq)) + if (link_freq != clk_round_rate(fsl_ldb->clk_ldb, link_freq)) + return MODE_NOCLOCK; + + /* Validate pixel clock rate. */ + pclk_rate = mode->clock * HZ_PER_KHZ; + rounded_pclk_rate = clk_round_rate(fsl_ldb->clk_pixel, pclk_rate); + if (rounded_pclk_rate != pclk_rate) return MODE_NOCLOCK; return MODE_OK; @@ -294,12 +303,20 @@ static const struct drm_bridge_funcs funcs = { .mode_valid = fsl_ldb_mode_valid, }; +static void fsl_ldb_clk_pixel_put(void *data) +{ + struct fsl_ldb *fsl_ldb = data; + + clk_put(fsl_ldb->clk_pixel); +} + static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *remote1, *remote2; + struct device_node *remote0, *remote1, *remote2; struct fsl_ldb *fsl_ldb; int dual_link; + int ret; fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL); if (!fsl_ldb) @@ -313,9 +330,23 @@ static int fsl_ldb_probe(struct platform_device *pdev) fsl_ldb->bridge.funcs = &funcs; fsl_ldb->bridge.of_node = dev->of_node; - fsl_ldb->clk = devm_clk_get(dev, "ldb"); - if (IS_ERR(fsl_ldb->clk)) - return PTR_ERR(fsl_ldb->clk); + fsl_ldb->clk_ldb = devm_clk_get(dev, "ldb"); + if (IS_ERR(fsl_ldb->clk_ldb)) + return PTR_ERR(fsl_ldb->clk_ldb); + + /* Get pixel clock from display controller's OF node. */ + remote0 = of_graph_get_remote_node(dev->of_node, 0, 0); + fsl_ldb->clk_pixel = of_clk_get_by_name(remote0, "pix"); + of_node_put(remote0); + if (IS_ERR(fsl_ldb->clk_pixel)) + return PTR_ERR(fsl_ldb->clk_pixel); + + ret = devm_add_action_or_reset(dev, fsl_ldb_clk_pixel_put, fsl_ldb); + if (ret) { + dev_err(dev, "Failed to add pixel clock put devm action: %d\n", + ret); + return ret; + } fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); if (IS_ERR(fsl_ldb->regmap)) -- 2.34.1
