Hi Maxime Thank you for your reply. > > The AST2700 is the 7th generation SoC from Aspeed, featuring three > > GPIO controllers that are support 64-bit DMA capability. > > Adding features is shown in the following list. > > 1.Support 64-bit DMA > > Add the high address (63:32) registers for description address and the > > description field for packet buffer with high address part. > > These registers and fields in legacy Aspeed SoC are reserved. > > This 64-bit DMA changing has verified on legacy Aspeed Soc, like > > AST2600. > > Maybe each of these features should be in a dedicated patch ? Agree. I will separate them into separate patches on next version. > > > 2.Set RMII pin strap in AST2700 compitable > compatible > > > Use bit 20 of MAC 0x50 to represent the pin strap of AST2700 RMII and > > RGMII. Set to 1 is RMII pin, otherwise is RGMII. > > This bis is also reserved in legacy Aspeed SoC. > > Signed-off-by: Jacky Chou <jacky_chou@xxxxxxxxxxxxxx> > > [...] > > > @@ -349,6 +354,10 @@ static void ftgmac100_start_hw(struct ftgmac100 > *priv) > > if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) > > maccr |= FTGMAC100_MACCR_RM_VLAN; > > > > + if (of_device_is_compatible(priv->dev->of_node, "aspeed,ast2700-mac") > && > > + priv->netdev->phydev->interface == PHY_INTERFACE_MODE_RMII) > > + maccr |= FTGMAC100_MACCR_RMII_ENABLE; > > The driver code takes the assumption that netdev->phydev might be NULL, I > think you should therefore add an extra check here as well before getting the > interface mode. Agree. I will add a check for netdev->phydev here. Perhaps it is null. Thanks, Jacky
