Hi Claudiu,
> -----Original Message-----
> From: Claudiu <claudiu.beznea@xxxxxxxxx>
> Sent: 13 November 2024 13:36
> Subject: [PATCH v3 22/25] arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node
>
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Add versa3 clock generator node. It provides the clocks for the Ethernet PHY, PCIe, audio devices.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> ---
>
> Changes in v3:
> - none
>
> Changes in v2:
> - none
>
> .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-
> smarc-som.dtsi
> index 2ed01d391554..6e58d47d85b0 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -92,6 +92,12 @@ vcc_sdhi2: regulator2 {
> gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + x3_clk: x3-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> };
>
> #if SW_CONFIG3 == SW_ON
> @@ -152,6 +158,30 @@ &extal_clk {
>
> &i2c1 {
> status = "okay";
> +
> + versa3: clock-generator@68 {
> + compatible = "renesas,5l35023";
> + reg = <0x68>;
> + clocks = <&x3_clk>;
> + #clock-cells = <1>;
> + assigned-clocks = <&versa3 0>,
> + <&versa3 1>,
> + <&versa3 2>,
> + <&versa3 3>,
> + <&versa3 4>,
> + <&versa3 5>;
> + assigned-clock-rates = <24000000>,
> + <12288000>,
> + <11289600>,
> + <25000000>,
> + <100000000>,
> + <100000000>;
> + renesas,settings = [
> + 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
> + 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
> + a0 80 30 30 9c
> + ];
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Cheers,
Biju
> + };
> };
>
> #if SW_CONFIG2 == SW_ON
> --
> 2.39.2
