Hi Claudiu,
> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
> Sent: 12 November 2024 08:31
> Subject: Re: [PATCH v2 24/25] arm64: dts: renesas: rzg3s-smarc: Enable SSI3
>
> Hi, Biju,
>
> On 11.11.2024 13:30, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
> >> Sent: 11 November 2024 11:20
> >> Subject: Re: [PATCH v2 24/25] arm64: dts: renesas: rzg3s-smarc:
> >> Enable SSI3
> >>
> >> Hi, Biju,
> >>
> >> On 10.11.2024 10:54, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>> Thanks for the patch.
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu <claudiu.beznea@xxxxxxxxx>
> >>>> Sent: 08 November 2024 10:50
> >>>> Subject: [PATCH v2 24/25] arm64: dts: renesas: rzg3s-smarc: Enable
> >>>> SSI3
> >>>>
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >>>>
> >>>> Enable SSI3.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >>>> ---
> >>>>
> >>>> Changes in v2:
> >>>> - none
> >>>>
> >>>> arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 26
> >>>> ++++++++++++++++++++
> >>>> 1 file changed, 26 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> >>>> b/arch/arm64/boot/dts/renesas/rzg3s-
> >>>> smarc.dtsi
> >>>> index 4aa99814b808..6dd439e68bd4 100644
> >>>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> >>>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
> >>>> @@ -64,6 +64,11 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
> >>>> };
> >>>> };
> >>>>
> >>>
> >>> &audio_clk1 {
> >>> assigned-clocks = <&versa3 xx>;
> >>> clock-frequency = <11289600>; };
> >>
> >> audio_clk1 node is in the RZ/G3S dtsi to keep the compilation happy.
> >>
> >> For this board the audio clock1 for the SSI 3 is from <&versa3 2>.
> >>
> >> If we fill in the audio_clk1 here it will be useless, there will be
> >> no consumers for it and it is not available on board.
> >
> > As per SSI IP needs external clks AUDIO_CLK1 and AUDIO_CLK2.
> >
> > AUDIO_CLK1 is provided by versa3 generator and
> > AUDIO_CLK2 is provided by Crystal.
> >
> > Currently AUDIO_CLK2 it reports a frequency of 12288000 which is a
> > multiple of 48kHz whereas for AUDIO_CLK1, it reports a frequency of 0.
>
> Why? You mentioned above that "AUDIO_CLK1 is provided by versa3 generator".
Output from versa3 generator is connector to AUDIO_CLK1 pin that you described in
SoC dtsi node with the entries
+ audio_clk1: audio-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ status = "disabled";
+ };
This needs to be overridden by board dts, where versa3 is providing this clk.
Currently there is no relation between this SoC device node and versa3 clk output for audio clk1.
Cheers,
Biju
