On 10/29/24 4:28 PM, Alexandre TORGUE wrote:
Hi Marek
On 10/17/24 21:09, Marek Vasut wrote:
The STM32MP13xx DHCOR SoM is populated with M24256E EEPROM which has
Additional Write lockable page at separate I2C address. Describe the
page in DT to make it available.
Note that the WLP page on this device is hardware write-protected by
R37 which pulls the nWC signal high to VDD_3V3_1V8 power rail.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx>
Cc: Christoph Niedermaier <cniedermaier@xxxxxxxxxxxxxxxxxx>
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: kernel@xxxxxxxxxxxxxxxxxx
Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: linux-stm32@xxxxxxxxxxxxxxxxxxxxxxxxxxxx
---
V2: Fix up the M25256E in Subject
---
DEPENDS:
- https://lore.kernel.org/linux-i2c/20241017184152.128395-1-
marex@xxxxxxx/
- https://lore.kernel.org/linux-i2c/20241017184152.128395-2-
marex@xxxxxxx/
---
arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/
arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
index 5c633ed548f37..07133bd82efa6 100644
--- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
@@ -202,6 +202,12 @@ eeprom0: eeprom@50 {
pagesize = <64>;
};
+ eeprom0wl: eeprom@58 {
+ compatible = "st,24256e-wl"; /* ST M24256E WL page of 0x50 */
+ pagesize = <64>;
+ reg = <0x58>;
+ };
+
You could have sorted nodes by I2C addresses.
Fixed in [PATCH] ARM: dts: stm32: Sort M24256E write-lockable page in DH
STM32MP13xx DHCOR SoM DT
Sorry.
(I also wrote me a sorting tool in the meantime, but it still isn't too
good)
