Samuel Holland wrote:
> JH7100 provides a physical memory region which is a noncached alias of
> normal cacheable DRAM. Now that Linux can apply PMAs by selecting
> between aliases of a physical memory region, any page of DRAM can be
> marked as noncached for use with DMA, and the preallocated DMA pool is
> no longer needed. This allows portable kernels to boot on JH7100 boards.
>
> Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx>
> ---
>
> arch/riscv/Kconfig.errata | 19 ------------
> .../boot/dts/starfive/jh7100-common.dtsi | 30 ++++---------------
> 2 files changed, 6 insertions(+), 43 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 2806ed7916c7..fc2c7fb2caff 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -53,25 +53,6 @@ config ERRATA_SIFIVE_CIP_1200
>
> If you don't know what to do here, say "Y".
>
> -config ERRATA_STARFIVE_JH7100
> - bool "StarFive JH7100 support"
> - depends on ARCH_STARFIVE
> - depends on !DMA_DIRECT_REMAP
> - depends on NONPORTABLE
> - select DMA_GLOBAL_POOL
Hi Samuel,
Thank you for working on this!
The JH7100 still need the RISCV_NONSTANDARD_CACHE_OPS from the sifive-ccache
driver for streaming DMA, so if I just remove the 3 lines above instead of the
whole ERRATE_STARFIVE_JH7110 (and enable RISCV_ISA_SVPBMT) this series works on
my Starlight board.
> - select RISCV_DMA_NONCOHERENT
> - select RISCV_NONSTANDARD_CACHE_OPS
> - select SIFIVE_CCACHE
> - default n
> - help
> - The StarFive JH7100 was a test chip for the JH7110 and has
> - caches that are non-coherent with respect to peripheral DMAs.
> - It was designed before the Zicbom extension so needs non-standard
> - cache operations through the SiFive cache controller.
> -
> - Say "Y" if you want to support the BeagleV Starlight and/or
> - StarFive VisionFive V1 boards.
> -
> config ERRATA_THEAD
> bool "T-HEAD errata"
> depends on RISCV_ALTERNATIVE
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> index ae1a6aeb0aea..34885fe40e2d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> @@ -9,8 +9,14 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/leds/common.h>
> #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
> +#include <dt-bindings/riscv/physical-memory.h>
>
> / {
> + riscv,physical-memory-regions =
> + <0x00 0x00000000 0x40 0x00000000 (PMA_RW | PMA_IO) 0x0>,
> + <0x00 0x80000000 0x08 0x00000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY) 0x0>,
> + <0x10 0x00000000 0x08 0x00000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY | PMR_ALIAS(1)) 0x0>;
> +
The size and placement of the DMA pool was kind of arbitrary but the above is
a feature of the SoC, so should be moved to jh7100.dtsi instead.
> aliases {
> mmc0 = &sdio0;
> mmc1 = &sdio1;
> @@ -42,30 +48,6 @@ led-ack {
> };
> };
>
> - reserved-memory {
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> -
> - dma-reserved@fa000000 {
> - reg = <0x0 0xfa000000 0x0 0x1000000>;
> - no-map;
> - };
> -
> - linux,dma@107a000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x10 0x7a000000 0x0 0x1000000>;
> - no-map;
> - linux,dma-default;
> - };
> - };
> -
> - soc {
> - dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
> - <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
> - <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
> - };
> -
> wifi_pwrseq: wifi-pwrseq {
> compatible = "mmc-pwrseq-simple";
> reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
> --
> 2.45.1
>
