On Thu, Oct 31, 2024 at 10:37:10AM +0530, Anup Patel wrote: > Hi Thomas, > > On Tue, Oct 29, 2024 at 1:16 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > > > > On Tue, Oct 22 2024 at 12:02, Inochi Amaoto wrote: > > > Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an > > > enhanced implementation of the RISC-V ACLINT SSWI specification. > > > This device allows the system to send ipi via fast device interface. > > > > > > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx> > > > > Can someone from the RISCV folks please confirm that thtis is good to > > go? > > The T-HEAD C900 ACLINT SSWI is not compliant to any RISC-V specification > so at this point it is a T-HEAD specific device. The RISC-V ACLINT SSWI > specification cited by this driver was never ratified by RISC-V international > in-favor of the ratified RISC-V AIA specification which has a much cleaner > way of doing IPI (as software injected MSIs) implemented by the IMSIC > driver and this also supports IPI virtualization. > > Since this is a T-HEAD specific implementation, the description in all > patches of this series should be updated to replace references of the > RISC-V ACLINT SSWI specification with publicly available T-HEAD > documentation. Once, this is done, I think this series can go ahead. > > Regards, > Anup Thanks for your kindly explanation. I will update all the description about these patch. Regards, Inochi
