On 10/25/24 2:14 PM, Peter Griffin wrote:
> HCI_IOP_ACG_DISABLE is an undocumented register in the TRM but the
> downstream driver sets this register so we follow suit here.
>
> The register is already 0 presumed to be set by the bootloader as
> the comment downstream implies the reset state is 1. So whilst this
> is a nop currently, it should help with suspend/resume.
It should help in case the bootloader changes I assume. I see
gs101_ufs_drv_init() gets called only at probe time, via
ufshcd_pltfrm_init().
>
> Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
Reviewed-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
> ---
> drivers/ufs/host/ufs-exynos.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index b0cbb147c7a1..fa4e61f152c4 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -76,6 +76,10 @@
> #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
> UNIPRO_PCLK_CTRL_EN |\
> UNIPRO_MCLK_CTRL_EN)
> +
> +#define HCI_IOP_ACG_DISABLE 0x100
> +#define HCI_IOP_ACG_DISABLE_EN BIT(0)
> +
> /* Device fatal error */
> #define DFES_ERR_EN BIT(31)
> #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
> @@ -220,10 +224,15 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs)
> static int gs101_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
> {
> struct ufs_hba *hba = ufs->hba;
> + u32 reg;
>
> /* Enable WriteBooster */
> hba->caps |= UFSHCD_CAP_WB_EN;
>
> + /* set ACG to be controlled by UFS_ACG_DISABLE */
> + reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE);
> + hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE);
> +
> return exynos_ufs_shareability(ufs);
> }
>
