On 9/12/24 13:55, Charlie Jenkins wrote: > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > vendor extension. I believe it's more advantageous to use RISCV_HWPROBE_KEY_VENDOR_EXT_0 to ensure that this key is shared with all vendors. Subsequently, mhartid can select the specific vendor. Each vendor can allocate its own extension space within the bitmask. Therefore, we won't require the addition of a new hardware probe key for a new vendor in the future. RISC-V C-API chooses a similar design. Link: https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask > This new key will allow userspace code to probe for which thead vendor > extensions are supported. This API is modeled to be consistent with > RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit > corresponding to a supported thead vendor extension of the cpumask set. > Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program > to determine all of the supported thead vendor extensions in one call. > Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> > Reviewed-by: Evan Green <evan@xxxxxxxxxxxx> > --- > arch/riscv/include/asm/hwprobe.h | 3 +- > .../include/asm/vendor_extensions/thead_hwprobe.h | 19 +++++++++++ > .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 3 +- > arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ > arch/riscv/kernel/sys_hwprobe.c | 5 +++ > arch/riscv/kernel/vendor_extensions/Makefile | 1 + > .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ > 8 files changed, 88 insertions(+), 2 deletions(-) > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index ef01c182af2b..6148e1eab64c 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > /* > - * Copyright 2023 Rivos, Inc > + * Copyright 2023-2024 Rivos, Inc > */ > #ifndef _ASM_HWPROBE_H > @@ -21,6 +21,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > case RISCV_HWPROBE_KEY_IMA_EXT_0: > case RISCV_HWPROBE_KEY_CPUPERF_0: > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > return true; > } > diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > new file mode 100644 > index 000000000000..65a9c5612466 > --- /dev/null > +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > + > +#include <linux/cpumask.h> > + > +#include <uapi/asm/hwprobe.h> > + > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); > +#else > +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, > + const struct cpumask *cpus) > +{ > + pair->value = 0; > +} > +#endif > + > +#endif > diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > new file mode 100644 > index 000000000000..6b9293e984a9 > --- /dev/null > +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > @@ -0,0 +1,37 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright 2024 Rivos, Inc > + */ > + > +#ifndef _ASM_RISCV_SYS_HWPROBE_H > +#define _ASM_RISCV_SYS_HWPROBE_H > + > +#include <asm/cpufeature.h> > + > +#define VENDOR_EXT_KEY(ext) \ > + do { \ > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + else \ > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + } while (false) > + > +/* > + * Loop through and record extensions that 1) anyone has, and 2) anyone > + * doesn't have. > + * > + * _extension_checks is an arbitrary C block to set the values of pair->value > + * and missing. It should be filled with VENDOR_EXT_KEY expressions. > + */ > +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_vendor_bitmap, _extension_checks) \ > + do { \ > + int cpu; \ > + u64 missing = 0; \ > + for_each_cpu(cpu, (cpus)) { \ > + struct riscv_isavendorinfo *isainfo = &(per_hart_vendor_bitmap)[cpu]; \ > + _extension_checks \ > + } \ > + (pair)->value &= ~missing; \ > + } while (false) \ > + > +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index b706c8e47b02..452d0b84f17f 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > /* > - * Copyright 2023 Rivos, Inc > + * Copyright 2023-2024 Rivos, Inc > */ > #ifndef _UAPI_ASM_HWPROBE_H > @@ -82,6 +82,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 > #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8 > +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 9 > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > /* Flags */ > diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h > new file mode 100644 > index 000000000000..43790ebe5faf > --- /dev/null > +++ b/arch/riscv/include/uapi/asm/vendor/thead.h > @@ -0,0 +1,3 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > + > +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 8d1b5c35d2a7..5a3dc8e66c85 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -15,6 +15,7 @@ > #include <asm/uaccess.h> > #include <asm/unistd.h> > #include <asm/vector.h> > +#include <asm/vendor_extensions/thead_hwprobe.h> > #include <vdso/vsyscall.h> > @@ -241,6 +242,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > pair->value = riscv_timebase; > break; > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > + hwprobe_isa_vendor_ext_thead_0(pair, cpus); > + break; > + > /* > * For forward compatibility, unknown keys don't fail the whole > * call, but get their element key set to -1 and value set to 0 > diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile > index 353522cb3bf0..866414c81a9f 100644 > --- a/arch/riscv/kernel/vendor_extensions/Makefile > +++ b/arch/riscv/kernel/vendor_extensions/Makefile > @@ -2,3 +2,4 @@ > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o > +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o > diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > new file mode 100644 > index 000000000000..2eba34011786 > --- /dev/null > +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include <asm/vendor_extensions/thead.h> > +#include <asm/vendor_extensions/thead_hwprobe.h> > +#include <asm/vendor_extensions/vendor_hwprobe.h> > + > +#include <linux/cpumask.h> > +#include <linux/types.h> > + > +#include <uapi/asm/hwprobe.h> > +#include <uapi/asm/vendor/thead.h> > + > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > +{ > + VENDOR_EXTENSION_SUPPORTED(pair, cpus, > + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { > + VENDOR_EXT_KEY(XTHEADVECTOR); > + }); > +}
