On 29/10/2024 12:30, Ram Kumar Dwivedi wrote:
> There are three allocators supported for inline crypto engine:
> Floor based, Static and Instantaneous allocator.
>
> Document the compatible used for the allocator configurations
> for inline crypto engine found.
>
> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@xxxxxxxxxxx>
> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@xxxxxxxxxxx>
> Co-developed-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
> Signed-off-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 25a5edeea164..069bd87d3404 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -108,6 +108,11 @@ properties:
> description:
> GPIO connected to the RESET pin of the UFS memory device.
>
> + ice-config:
> + type: object
> + description:
> + ICE configuration table for Qualcom SOC
Not much improved, still not constrained, this can be literally
anything, right? No explanation what this is.
This does not look even like hardware property, although with such
explanation tricky to judge.
NAK, please reach internally to qcom folks so they will guide you how
bindings should look like. You are *not supposed* to send downstream
stuff to us.
> +
> required:
> - compatible
> - reg
> @@ -350,5 +355,24 @@ examples:
> <0 0>,
> <0 0>;
> qcom,ice = <&ice>;
> +
> + ice_cfg: ice-config {
> + static-alloc {
> + ice-allocator-name = "static-alloc";
> + rx-alloc-percent = <60>;
> + status = "okay";
Drop. Same everywhere else.
Best regards,
Krzysztof
