On Mon, Oct 28, 2024 at 11:54:12AM +0100, Francesco Dolcini wrote: > From: Parth Pancholi <parth.pancholi@xxxxxxxxxxx> > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > host controller. The controller supports software configuration > through PCIe registers, such as controlling the PWRONx polarity > via the USB control register (E0h). > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > Signed-off-by: Parth Pancholi <parth.pancholi@xxxxxxxxxxx> > Signed-off-by: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx> > --- > v4: > - add $ref: usb-xhci.yaml > - description: wrap to 80 columns, add that the two variants use the > same device ID > - revise the example, based on comment from Rob and taking > marvell,prestera.yaml as an example (this binding was reviewed and > amended by Rob in the past). > v3: use lowercase hex in compatible > v2: rename property to ti,tusb7320-pwron-active-high and change type to flag > --- > .../bindings/usb/ti,tusb73x0-pci.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > new file mode 100644 > index 000000000000..e98a2e0bfcbb > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) > + > +maintainers: > + - Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx> > + > +description: > + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. > + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up > + to four downstream ports, both variants share the same PCI device ID. > + > +properties: > + compatible: > + const: pci104c,8241 > + > + reg: > + maxItems: 1 > + > + ti,tusb7320-pwron-active-high: Drop tusb7320. There is never device name in property name, because it is redundant and makes it completely not-reusable. > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Configure the polarity of the PWRONx# signals. When this is present, the > + PWRONx# pins are active high and their internal pull-down resistors are > + disabled. When this is absent, the PWRONx# pins are active low (default) > + and their internal pull-down resistors are enabled. Best regards, Krzysztof
