From: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> This adds DCSS + MHDP + MHDP PHY nodes. PHY mode (DP/HDMI) is selected by the connector type connected to mhdp port@1 endpoint. Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> --- v17->v18: *No change arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d51de8d899b2b..df8ba1d5391ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1602,6 +1602,74 @@ aips4: bus@32c00000 { /* AIPS4 */ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + mdhp_phy: phy@32c00000 { + compatible = "fsl,imx8mq-hdptx-phy"; + reg = <0x32c00000 0x100000>; + #phy-cells = <0>; + clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ref", "apb"; + }; + + mhdp: bridge@32c00000 { + compatible = "fsl,imx8mq-mhdp8501"; + reg = <0x32c00000 0x100000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + phys = <&mdhp_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mhdp_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + + mhdp_out: endpoint { + }; + }; + }; + }; + + dcss: display-controller@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupt-parent = <&irqsteer>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + + port { + dcss_out: endpoint { + remote-endpoint = <&mhdp_in>; + }; + }; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; -- 2.34.1